In transistor level layout (e.g., of a metal oxide semiconductor (MOS) transistor), a length of diffusion (LOD) refers to an amount by which a diffusion region between source and drain terminals of the transistor extends away from a gate terminal. An LOD effect refers to stress induced on the MOS transistor based on the LOD. In general, a smaller LOD causes greater stress or in other words, has a worse LOD effect, while increasing or improving the LOD can lead to performance improvements.
It is difficult to completely mitigate LOD effect on transistors in a transistor level layout using standard logic cells and placement techniques. Some techniques to mitigate the LOD effect focus on extending the diffusion region, where possible, with left and right diffusion edges configured to share common electrical junctions (e.g., power and ground connections). However, extending the diffusion region in this manner may hinder cell placement methodologies which attempt to place logic cells of equal or comparable physical footprints (also measured in terms of cell pitch or width of the diffusion layers) in a manner which results in logic cells being abutted or adjoined. Such abutment can enable sharing of diffusion edges between adjoining cells and potentially increase the effective LOD of adjoining cells. However, logic cell placement to improve diffusion edge sharing in this manner may not be feasible in some conventional designs using standard logic cell libraries.
For example, considering Fin Field Effect Transistor (or “finfet”) technologies wherein a common gate terminal (e.g., made of polysilicon or “poly” material or some other material including metal) may be shared among two or more fins. Source and drain terminals of the finfets are formed by connecting common diffusion regions formed underneath the fins to power supply rails (e.g., Vdd and ground) or other common nodes. The common poly may also be shared amongst multiple finfets. Finfet logic libraries may include logic cells with different fin counts. If the diffusion regions of some fins can be extended as noted above, the logic libraries may include logic cells with non-uniform lengths of diffusion regions, which means that some fins of adjoining cells may not be able to share their diffusion regions with neighboring cells. Further, a lateral width of diffusion (in a transverse direction to the length of diffusion) varies proportionally with the number of fins of each logic cell in a logic cell layout. While conventional layout techniques may allow for abutment of logic cells with the same number of fins or the same width, such techniques may not permit placement of two cells with different fin counts in a manner which could have allowed for sharing diffusion regions.
However, with fixed fin counts, integrating circuits requiring different fin counts becomes difficult to realize. This is because conventional techniques do not support fin stepping (i.e., abutting cells with different fin counts to share a common diffusion), which may be desirable in ratio based logic. Ratio based logic is conventionally encountered in designs comprising p-channel FETs (or simply, “pfets”) and n-channel FETs (or “nfets”). For example, a 2-input NAND gate design may include two 4-fin nfets coupled in series between output and ground terminals (effectively forming 4 fins) and two 2-fin pfets coupled in parallel with one another and connected between supply voltage Vdd and the output (effectively forming 2 fins). The size of the nfets (i.e., in terms of their fin counts) is designed to be twice the size of their counterpart pfets as discussed above in order to achieve balanced output transitions and delays for both rising and falling inputs to the 2-input NAND gate. A similar ratio in terms of fin counts of component logic cells may also be used for other standard cells such as a 2-input NOR gate designed with finfet technology.
Since fin stepping is not supported in conventional designs, separate diffusion domains may be provided for logic cells with different fin counts, e.g., in the design of logic gates such as the 2-input NAND gate discussed above. However, restricting the design to having separate diffusion domains may foreclose the possibility of sharing a common diffusion edge between two cells with different fin counts. In an effort to integrate logic cells with different fin counts, conventional designs may include breaks in the diffusion regions for the nfets and pfets, and sometimes even within a cell, e.g. in the case of a 2-input AND gate). As understood from the foregoing discussion, breaks in the diffusion region can result in short LODs or adversely impact the LOD effects.
Accordingly, a need in the art is recognized for logic cell designs which can support ratio based logic while also avoiding the LOD effects which may arise due to diffusion breaks.